CUED Publications database

Tellurium nanowire gate-all-around MOSFETs for Sub-5 nm applications

Yin, Y and Zhang, Z and Zhong, H and Shao, C and Wan, X and Zhang, C and Robertson, J and Guo, Y (2021) Tellurium nanowire gate-all-around MOSFETs for Sub-5 nm applications. ACS Applied Materials and Interfaces, 13. pp. 3387-3396. ISSN 1944-8244

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Abstract

The nanowire (NW) and gate-all-around (GAA) technologies are regarded as the ultimate solutions to sustain Moore's law benefitting from the exceptional gate control ability. Herein, we conduct a comprehensive ab initio quantum transportation calculation at different diameters (single trigonal-tellurium NW (1Te) and three trigonal-tellrium NW (3Te)) sub-5 nm tellurium (Te) GAA NW metal-oxide-semiconductor field-effect transistors (MOSFETs). The results claim that the performance of 1Te FETs is superior to that of 3Te FETs. Encouragingly, the single Te (1Te) n-type MOSFET with 5 nm gate length achieves International Technology Roadmap for Semiconductors (ITRS) high-performance (HP) and low-dissipation (LP) goals simultaneously. Especially, the HP on-state current reaches 6479 μA/μm, 7 times higher than the goal (900 μA/μm). Moreover, the subthreshold swing of the n-type 1Te FETs even hits a thermionic limit of 60 mV/dec. In terms of the spin-orbit coupling effect, the drain currents of devices are further improved, particularly the p-type Te FETs can also achieve the ITRS HP goal. Hence, the GAA Te MOSFETs provide a feasible approach for state-of-the-art sub-5 nm device applications.

Item Type: Article
Uncontrolled Keywords: Tellurium nanowire carrier mobility gate-all-around MOSFETs quantum transport calculations sub-5 nm FET
Subjects: UNSPECIFIED
Divisions: UNSPECIFIED
Depositing User: Cron Job
Date Deposited: 29 Jan 2021 22:08
Last Modified: 13 Apr 2021 10:48
DOI: 10.1021/acsami.0c18767