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Normally-off LPCVD-SiNx/GaN MIS-FET with crystalline oxidation interlayer

Hua, M and Wei, J and Tang, G and Zhang, Z and Qian, Q and Cai, X and Wang, N and Chen, KJ (2017) Normally-off LPCVD-SiNx/GaN MIS-FET with crystalline oxidation interlayer. IEEE Electron Device Letters, 38. pp. 929-932. ISSN 0741-3106

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Developing effective technique to protect the etched- GaN surface from the degradation in a hightemperature (i.e., at ∼ 780°C) process, such as lowpressure chemical vapor deposition (LPCVD), is essential for fabricating normally-off GaN MIS-FETs with high-quality dielectric/GaN interface and highly reliable gate dielectric. In this letter, we developed an approach of obtaining such a protection layer using oxygen-plasma treatment followed by in situ annealing prior to the LPCVD-SiN deposition. A sharp and stable crystalline oxidation interlayer (COIL) between the LPCVD-SiN and etched-GaN was successfully formed. The LPCVD-SiN /GaN MIS-FETs with COIL deliver normally-off operation with a VTH of 1.15 V, small ON-resistance, small hysteresis, and thermally stable VTH. x x x

Item Type: Article
Depositing User: Cron Job
Date Deposited: 25 Jan 2021 20:04
Last Modified: 15 Apr 2021 06:04
DOI: 10.1109/LED.2017.2707473