CUED Publications database

Partial soi power LDMOS with a variable low-kappa; Dielectric buried layer and a buried P layer

Luo, X and Udrea, F and Wang, Y and Yao, G and Liu, Y (2010) Partial soi power LDMOS with a variable low-kappa; Dielectric buried layer and a buried P layer. IEEE Electron Device Letters, 31. pp. 594-596. ISSN 0741-3106

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Abstract

A power LDMOS on partial silicon on insulator (PSOI) with a variable low-κ dielectric (VLKD) buried layer and a buried p (BP) layer is proposed (VLKD BPSOI). At a low κ value, the electric field strength in the buried dielectric (EI) is enhanced, and a Si window makes the substrate share the vertical voltage drop, leading to a high vertical breakdown voltage (BV). Moreover, three interface field peaks are introduced by the BP, the Si window, and the VLKD, which modulate the fields in the SOI layer, the VLKD layer, and the substrate; consequently, a high BV is obtained. Furthermore, the BP reduces the specific on-resistance (Ron), and the Si window alleviates the self-heating effect (SHE). The BV for VLKD BPSOI is enhanced by 34.5%, and Ron is decreased by 26.6%, compared with those for the conventional PSOI, and VLKD BPSOI also maintains a low SHE. © 2006 IEEE.

Item Type: Article
Uncontrolled Keywords: Breakdown voltage (BV) Buried layer Electric field Low-$k$ dielectric Silicon on insulator (SOI)
Subjects: UNSPECIFIED
Divisions: Div B > Electronics, Power & Energy Conversion
Depositing User: Cron Job
Date Deposited: 07 Mar 2014 11:50
Last Modified: 08 Dec 2014 02:31
DOI: 10.1109/LED.2010.2046616