Yang, HG and Holburn, DM (1989) Semi-analytic slope delay model for CMOS switch-level timing verification. Proceedings - IEEE International Symposium on Circuits and Systems, 3. pp. 2032-2035. ISSN 0271-4310Full text not available from this repository.
A novel slope delay model for CMOS switch-level timing verification is presented. It differs from conventional methods in being semianalytic in character. The model assumes that all input waveforms are trapezoidal in overall shape, but that they vary in their slope. This simplification is quite reasonable and does not seriously affect precision, but it facilitates rapid solution. The model divides the stages in a switch-level circuit into two types. One corresponds to the logic gates, and the other corresponds to logic gates with pass transistors connected to their outputs. Semianalytic modeling for both cases is discussed.
|Divisions:||Div B > Solid State Electronics and Nanoscale Science|
|Depositing User:||Unnamed user with email email@example.com|
|Date Deposited:||09 Dec 2016 17:45|
|Last Modified:||24 Mar 2017 22:50|