CUED Publications database

Semi-analytic slope delay model for CMOS switch-level timing verification

Yang, HG and Holburn, DM (1989) Semi-analytic slope delay model for CMOS switch-level timing verification. Proceedings - IEEE International Symposium on Circuits and Systems, 3. pp. 2032-2035. ISSN 0271-4310

Full text not available from this repository.
Item Type: Article
Subjects: UNSPECIFIED
Divisions: Div B > Solid State Electronics and Nanoscale Science
Depositing User: Cron Job
Date Deposited: 17 Jul 2017 19:04
Last Modified: 27 Jul 2017 06:42
DOI: