Yang, HG and Holburn, DM (1989) Semi-analytic slope delay model for CMOS switch-level timing verification. Proceedings - IEEE International Symposium on Circuits and Systems, 3. pp. 2032-2035. ISSN 0271-4310
Full text not available from this repository.| Item Type: | Article |
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| Subjects: | UNSPECIFIED |
| Divisions: | UNSPECIFIED |
| Depositing User: | Cron Job |
| Date Deposited: | 28 Oct 2011 16:37 |
| Last Modified: | 11 Mar 2013 01:48 |
| DOI: |
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