CUED Publications database

Switch-level timing verification for CMOS circuits. A semianalytic approach

Yang, H-G and Holburn, DM (1990) Switch-level timing verification for CMOS circuits. A semianalytic approach. IEE proceedings. Part G. Electronic circuits and systems, 137. pp. 405-412. ISSN 0143-7089

Full text not available from this repository.
Item Type: Article
Subjects: UNSPECIFIED
Divisions: Div B > Solid State Electronics and Nanoscale Science
Depositing User: Cron Job
Date Deposited: 07 Mar 2014 11:51
Last Modified: 17 Mar 2014 14:59
DOI: