Yang, H-G and Holburn, DM (1990) Switch-level timing verification for CMOS circuits. A semianalytic approach. IEE proceedings. Part G. Electronic circuits and systems, 137. pp. 405-412. ISSN 0143-7089Full text not available from this repository.
The paper describes a semianalytic slope delay model for CMOS switch-level timing verification. It is characterised by classification of the effects of the input slope, internal size and load capacitance of a logic gate on delay time, and then the use of a series of carefully chosen analytic functions to estimate delay times under different circumstances. In the field of VLSI analysis, this model achieves improvements in speed and accuracy compared with conventional approaches to transistor-level and switch-level simulation.
|Divisions:||Div B > Solid State Electronics and Nanoscale Science|
|Depositing User:||Cron Job|
|Date Deposited:||07 Mar 2014 11:51|
|Last Modified:||26 Jan 2015 03:19|