Yang, HG and Holburn, DM (1992) Hierarchical approach to timing verification in CMOS VLSI design. pp. 265-270.
Full text not available from this repository.| Item Type: | Article |
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| Subjects: | UNSPECIFIED |
| Divisions: | UNSPECIFIED |
| Depositing User: | Cron Job |
| Date Deposited: | 28 Oct 2011 16:37 |
| Last Modified: | 23 Jan 2012 01:34 |
| DOI: |
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