CUED Publications database

Hierarchical approach to timing verification in CMOS VLSI design

Yang, HG and Holburn, DM (1992) Hierarchical approach to timing verification in CMOS VLSI design. pp. 265-270.

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Item Type: Article
Subjects: UNSPECIFIED
Divisions: Div B > Solid State Electronics and Nanoscale Science
Depositing User: Cron Job
Date Deposited: 07 Mar 2014 12:39
Last Modified: 17 Mar 2014 14:59
DOI: