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Hierarchical approach to timing verification in CMOS VLSI design

Yang, HG and Holburn, DM (1992) Hierarchical approach to timing verification in CMOS VLSI design. pp. 265-270.

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Abstract

This paper describes a novel hierarchical approach to timing verification. Four types of relationship existing among signal paths are distinguished, based on a classification of the degree of interdependency in the circuit. In this way, irrelevant path delays can be excluded through consideration of the interaction between critical paths and others. Furthermore, under suitable conditions, bounded delay values for large hierarchical systems can be deduced using bounded delays determined for their constituent cells. Finally, we discuss the impact on design strategy of the hierarchical delay model presented in this paper.

Item Type: Article
Subjects: UNSPECIFIED
Divisions: Div B > Solid State Electronics and Nanoscale Science
Depositing User: Cron Job
Date Deposited: 07 Mar 2014 12:39
Last Modified: 26 Nov 2014 19:06
DOI: