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Hierarchical approach to timing verification in CMOS VLSI design

Yang, HG and Holburn, DM (1992) Hierarchical approach to timing verification in CMOS VLSI design. pp. 265-270.

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This paper describes a novel hierarchical approach to timing verification. Four types of relationship existing among signal paths are distinguished, based on a classification of the degree of interdependency in the circuit. In this way, irrelevant path delays can be excluded through consideration of the interaction between critical paths and others. Furthermore, under suitable conditions, bounded delay values for large hierarchical systems can be deduced using bounded delays determined for their constituent cells. Finally, we discuss the impact on design strategy of the hierarchical delay model presented in this paper.

Item Type: Article
Depositing User: Cron job
Date Deposited: 16 Jul 2015 14:15
Last Modified: 10 Oct 2015 06:17