Yang, HG and Holburn, DM (1992) Hierarchical approach to timing verification in CMOS VLSI design. pp. 265-270.Full text not available from this repository.
This paper describes a novel hierarchical approach to timing verification. Four types of relationship existing among signal paths are distinguished, based on a classification of the degree of interdependency in the circuit. In this way, irrelevant path delays can be excluded through consideration of the interaction between critical paths and others. Furthermore, under suitable conditions, bounded delay values for large hierarchical systems can be deduced using bounded delays determined for their constituent cells. Finally, we discuss the impact on design strategy of the hierarchical delay model presented in this paper.
|Divisions:||Div B > Solid State Electronics and Nanoscale Science|
|Depositing User:||Unnamed user with email firstname.lastname@example.org|
|Date Deposited:||18 May 2016 19:10|
|Last Modified:||28 Jul 2016 06:58|