CUED Publications database

Standard cell automated layout for a CMOS 50 MHz 8 × 8 bit pipelined parallel dadda multiplier

Crawley, DG and Amaratunga, GAJ (1988) Standard cell automated layout for a CMOS 50 MHz 8 × 8 bit pipelined parallel dadda multiplier. Proceedings - IEEE International Symposium on Circuits and Systems, 1. pp. 977-980. ISSN 0271-4310

Full text not available from this repository.
Item Type: Article
Subjects: UNSPECIFIED
Divisions: Div B > Electronics, Power & Energy Conversion
Depositing User: Cron Job
Date Deposited: 17 Jul 2017 19:52
Last Modified: 25 Jul 2017 05:48
DOI: