CUED Publications database

Standard cell automated layout for a CMOS 50 MHz 8 × 8 bit pipelined parallel dadda multiplier

Crawley, DG and Amaratunga, GAJ (1988) Standard cell automated layout for a CMOS 50 MHz 8 × 8 bit pipelined parallel dadda multiplier. Proceedings - IEEE International Symposium on Circuits and Systems, 1. pp. 977-980. ISSN 0271-4310

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Item Type: Article
Subjects: UNSPECIFIED
Divisions: Div B > Electronics, Power & Energy Conversion
Depositing User: Cron Job
Date Deposited: 07 Mar 2014 12:09
Last Modified: 10 Mar 2014 16:11
DOI:

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