Lim, HT and Udrea, F and Milne, W and Garner, D (1998) Switching speed enhancement of the LDMOSFETs using partial-SOI technology. IEEE International SOI Conference. pp. 53-54.Full text not available from this repository.
To overcome reduced breakdown voltage and self-heating effects inherent in silicon-on-insulator (SOI) power integrated circuits while still maintaining good isolation between low power CMOS circuits and the high power cells, partial SOI (PSOI) technology has been proposed. PSOI devices make use of both buried oxide and substrate depletion to support the breakdown voltage. 2D analyses and modeling of parasitic capacitances in PSOI structures show that PSOI-lightly doped MOSFETs can increase the switching speed by as much as four times compared to conventional SOI structures, making them very attractive for high switching applications.
|Depositing User:||Cron job|
|Date Deposited:||04 Feb 2015 23:08|
|Last Modified:||01 May 2015 18:53|