CUED Publications database

Switching speed enhancement of the LDMOSFETs using partial-SOI technology

Lim, HT and Udrea, F and Milne, W and Garner, D (1998) Switching speed enhancement of the LDMOSFETs using partial-SOI technology. IEEE International SOI Conference. pp. 53-54.

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Abstract

To overcome reduced breakdown voltage and self-heating effects inherent in silicon-on-insulator (SOI) power integrated circuits while still maintaining good isolation between low power CMOS circuits and the high power cells, partial SOI (PSOI) technology has been proposed. PSOI devices make use of both buried oxide and substrate depletion to support the breakdown voltage. 2D analyses and modeling of parasitic capacitances in PSOI structures show that PSOI-lightly doped MOSFETs can increase the switching speed by as much as four times compared to conventional SOI structures, making them very attractive for high switching applications.

Item Type: Article
Subjects: UNSPECIFIED
Divisions: Div B > Electronics, Power & Energy Conversion
Depositing User: Cron Job
Date Deposited: 07 Mar 2014 12:00
Last Modified: 27 Nov 2014 19:23
DOI: