Serrano-Gotarredona, T and Linares-Barranco, B and Agnus, G and Derycke, V and Bourgoin, J-P and Alibart, F and Vuillaume, D and Sohn, J and Bendall, J and Welland, ME and Gamrat, C (2009) Fast and compact simulation models for a variety of FET nano devices by the CMOS EKV equations. 2009 9th IEEE Conference on Nanotechnology, IEEE NANO 2009. pp. 691-694.Full text not available from this repository.
In this paper we explore the possibility of using the equations of a well known compact model for CMOS transistors as a parameterized compact model for a variety of FET based nano-technology devices. This can turn out to be a practical preliminary solution for system level architectural researchers, who could simulate behaviourally large scale systems, while more physically based models become available for each new device. We have used a four parameter version of the EKV model equations and verified that fitting errors are similar to those when using them for standard CMOS FET transistors. The model has been used for fitting measured data from three types of FET nano-technology devices obeying different physics, for different fabrication steps, and under different programming conditions. © 2009 IEEE NANO Organizers.
|Uncontrolled Keywords:||Circuit simulation EKV equations Nano-technology User modelling|
|Divisions:||Div B > Solid State Electronics and Nanoscale Science|
|Depositing User:||Cron Job|
|Date Deposited:||07 Mar 2014 12:34|
|Last Modified:||30 Nov 2014 21:46|