Zuo, D and Kelly, MJ (2012) Estimating and Enhancing the Yield of Tuneling SRAM Cells by Simulation. IEEE Electron Device Letters.
Full text not available from this repository.Abstract
As a novel implementation of the static random access memory (SRAM), the tunneling SRAM (TSRAM) uses the negative differential resistance of tunnel diodes (TD’s) and potentially offers considerable improvements in both standby power dissipation and integration density compared to the conventional CMOS SRAM. TSRAM has not yet been realized with a useful bit capacity mainly because the level of uniformity required of the nanoscale TD’s has been demanding and difficult to achieve. In this letter, we propose a Monte Carlo approach for estimating the yield of TSRAM cells and show that by optimizing the cell’s external circuit parameters, we can relax the allowable tolerance of a key device parameter of a resonant-TD-(RTD) based cell by three times.
| Item Type: | Article |
|---|---|
| Additional Information: | We have shown how, over 20 years after initially promised, and with advanced in MBE growth, that is may now be feasible to manufacture memory cells that use a pair of resonant tunnelling diodes as capacitors which have a great improvement over conventional SRAM cells. Our simulation study picks out the key characteristics of the diode performance that must be controlled, and how it is just now being achieved in practice. Discussions are being had with manufacturers about the next steps to take this idea from the lab towards production. |
| Subjects: | UNSPECIFIED |
| Divisions: | UNSPECIFIED |
| Depositing User: | Cron Job |
| Date Deposited: | 05 Jan 2012 12:10 |
| Last Modified: | 09 Jan 2012 01:06 |
| DOI: |
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