Alimadadi, M and Sheikhaei, S and Lemieux, G and Palmer, P and Mirabbasi, S and Dunford, W (2008) A 660MHz ZVS DC-DC converter using gate-driver charge-recycling in 0.18μm CMOS with an integrated output filter. PESC Record - IEEE Annual Power Electronics Specialists Conference. pp. 140-146. ISSN 0275-9306Full text not available from this repository.
The design and manufacture of a prototype chip level power supply is described, with both simulated and experimental results. Of particular interest is the inclusion of a fully integrated on-chip LC filter. A high switching frequency of 660MHz and the design of a device drive circuit reduce losses by supply stacking, low-swing signaling and charge recycling. The paper demonstrates that a chip level converter operating at high frequency can be built and shows how this can be achieved, using zero voltage switching techniques similar to those commonly used in larger converters. Both simulations and experimental data from a fabricated circuit in 0.18μm CMOS are included. The circuit converts 2.2V to 0.75∼1.0V at ∼55mA. ©2008 IEEE.
|Divisions:||Div B > Electronics, Power & Energy Conversion|
|Depositing User:||Cron Job|
|Date Deposited:||09 Dec 2016 18:15|
|Last Modified:||30 Mar 2017 08:51|