CUED Publications database

Low on-resistance SOI dual-trench-gate MOSFET

Luo, X and Lei, TF and Wang, YG and Yao, GL and Jiang, YH and Zhou, K and Wang, P and Zhang, ZY and Fan, J and Wang, Q and Ge, R and Zhang, B and Li, Z and Udrea, F (2012) Low on-resistance SOI dual-trench-gate MOSFET. IEEE Transactions on Electron Devices, 59. pp. 504-509. ISSN 0018-9383

Full text not available from this repository.


A low specific on-resistance (R-{{\rm on}, {\rm sp}}) integrable silicon-on-insulator (SOI) MOSFET is proposed, and its mechanism is investigated by simulation. The SOI MOSFET features double trenches and dual gates (DTDG SOI): an oxide trench in the drift region, a buried gate inset in the oxide trench, and another trench gate (TG) extended to a buried oxide layer. First, the dual gates form dual conduction channels, and the extended gate widens the vertical conduction area; both of which sharply reduce R-{{\rm on}, {\rm sp}}. Second, the oxide trench folds the drift region in the vertical direction, resulting in a reduced device pitch and R-{{\rm on}, {\rm sp}}. Third, the oxide trench causes multidirectional depletion. This not only enhances the reduced surface field effect and thus reshapes the electric field distribution but also increases the drift doping concentration, leading to a reduced R-{{\rm on}, {\rm sp}} and an improved breakdown voltage (BV). Compared with a conventional SOI lateral Double-diffused metal oxide semiconductor (LDMOS), the DTDG MOSFET increases BV from 39 to 92 V at the same cell pitch or decreases R-{{\rm on}, { \rm sp}} by 77% at the same BV by simulation. Finally, the TG extended sync hronously acts as an isolation trench between the high/low-voltage regions in a high-voltage integrated circuit, saving the chip area and simplifying the isolation process. © 2006 IEEE.

Item Type: Article
Divisions: Div B > Electronics, Power & Energy Conversion
Depositing User: Cron Job
Date Deposited: 17 Jul 2017 19:08
Last Modified: 08 Aug 2017 01:51