Rafiq, MA and Rafiq, MA and Rafiq, MA and Masubuchi, K and Durrani, ZAK and Durrani, ZAK and Colli, A and Mizuta, H and Mizuta, H and Milne, WI and Milne, WI and Oda, S and Oda, S (2012) Conduction bottleneck in silicon nanochain single electron transistors operating at room temperature. Japanese Journal of Applied Physics, 51. ISSN 0021-4922Full text not available from this repository.
Single electron transistors are fabricated on single Si nanochains, synthesised by thermal evaporation of SiO solid sources. The nanochains consist of one-dimensional arrays of ~10nm Si nanocrystals, separated by SiO 2 regions. At 300 K, strong Coulomb staircases are seen in the drain-source current-voltage (I ds-V ds) characteristics, and single-electron oscillations are seen in the drain-source current-gate voltage (I ds-V ds) characteristics. From 300-20 K, a large increase in the Coulomb blockade region is observed. The characteristics are explained using singleelectron Monte Carlo simulation, where an inhomogeneous multiple tunnel junction represents a nanochain. Any reduction in capacitance at a nanocrystal well within the nanochain creates a conduction " bottleneck", suppressing current at low voltage and improving the Coulomb staircase. The single-electron charging energy at such an island can be very high, ~20k BT at 300 K. © 2012 The Japan Society of Applied Physics.
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|Date Deposited:||16 Jul 2015 13:14|
|Last Modified:||28 Aug 2015 02:12|