Tan, MLP and Lentaris, G and Amaratunga, GAJ (2012) Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET. Nanoscale Research Letters, 7. ISSN 1931-7573Full text not available from this repository.
The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. © 2012 Tan et al.
|Uncontrolled Keywords:||Benchmarking CNTFET Device modeling HSPICE Logic gates MOSFET|
|Depositing User:||Cron job|
|Date Deposited:||16 Jul 2015 13:29|
|Last Modified:||04 Oct 2015 03:58|