CUED Publications database

Encapsulation of graphene transistors and vertical device integration by interface engineering with atomic layer deposited oxide

Alexander-Webber, JA and Sagade, AA and Aria, AI and Van Veldhoven, ZA and Braeuninger-Weimer, P and Wang, R and Cabrero-Vilatela, A and Martin, MB and Sui, J and Connolly, MR and Hofmann, S (2017) Encapsulation of graphene transistors and vertical device integration by interface engineering with atomic layer deposited oxide. 2D Materials, 4.

Full text not available from this repository.

Abstract

© 2016 IOP Publishing Ltd. We demonstrate a simple, scalable approach to achieve encapsulated graphene transistors with negligible gate hysteresis, low doping levels and enhanced mobility compared to as-fabricated devices. We engineer the interface between graphene and atomic layer deposited (ALD) Al 2 O 3 by tailoring the growth parameters to achieve effective device encapsulation whilst enabling the passivation of charge traps in the underlying gate dielectric. We relate the passivation of charge trap states in the vicinity of the graphene to conformal growth of ALD oxide governed by in situ gaseous H 2 O pretreatments. We demonstrate the long term stability of such encapsulation techniques and the resulting insensitivity towards additional lithography steps to enable vertical device integration of graphene for multi-stacked electronics fabrication.

Item Type: Article
Subjects: UNSPECIFIED
Divisions: Div B > Solid State Electronics and Nanoscale Science
Depositing User: Cron Job
Date Deposited: 17 Jul 2017 18:57
Last Modified: 21 Sep 2017 01:36
DOI: