CUED Publications database

Benchmarking of Homojunction Strained-Si NW Tunnel FETs for Basic Analog Functions

Biswas, A and Luong, GV and Chowdhury, MF and Alper, C and Zhao, QT and Udrea, F and Mantl, S and Ionescu, AM (2017) Benchmarking of Homojunction Strained-Si NW Tunnel FETs for Basic Analog Functions. IEEE Transactions on Electron Devices, 64. pp. 1441-1448. ISSN 0018-9383

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Abstract

© 2017 IEEE. This paper reports a compact ambipolar model for homojunction strained-silicon (sSi) nanowire (NW) tunnel FETs (TFETs) capable of accurately describing both I-V and G-V characteristics in all regimes of operation, n- A nd p-ambipolarity, the superlinear onset of the output characteristics, and the temperature dependence. Experimental calibration on long channel (350 nm) complementary n- A nd p-type sSi NW TFETs has been performed to create the model, which is used to systematically benchmark the main analog figures of merit at device level: G m /I d , g m /g ds , f T and f T/Id V d , and their temperature dependence from 25 °C to 125 °C. This allows for a direct comparison between 28-nm low-power Fully Depleted Silicon on Insulator (FD-SOI) CMOS node and 28-nm double-gate (DG) TFET. We demonstrate unique advantages of sSi DG TFET over CMOS, in terms of: 1) reduced temperature dependence of subthreshold swing; 2) higher transconductance per unit of current with peaks close to 40 V -1 , for currents lower than 10 nA/μm; and 3) higher unity gain frequency per unit power for currents below 10 nA/μm}.

Item Type: Article
Subjects: UNSPECIFIED
Divisions: Div B > Electronics, Power & Energy Conversion
Depositing User: Cron Job
Date Deposited: 17 Jul 2017 19:21
Last Modified: 08 Aug 2017 01:50
DOI: