CUED Publications database

High-speed binary multiplier

Kingsbury, NG (1971) High-speed binary multiplier. Electronics Letters, 7. pp. 277-278. ISSN 0013-5194

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A multiplier is described which uses a ‘tree’ of adders to add the partial products, resulting in a considerable increase in speed when the adders have a carry-propagation delay per bit which is appreciably less than the addition delay. © 1971, The Institution of Electrical Engineers. All rights reserved.

Item Type: Article
Divisions: Div F > Signal Processing and Communications
Depositing User: Cron Job
Date Deposited: 03 Aug 2017 02:37
Last Modified: 22 May 2018 08:09