CUED Publications database

Co-design/simulation of flip-chip assembly for high voltage IGBT packages

Rajaguru, P and Bailey, C and Lu, H and Aliyu, AM and Castellazzi, A and Pathirana, V and Udugampola, N and Trajkovic, T and Udrea, F and Mitcheson, PD and Elliott, ADT (2017) Co-design/simulation of flip-chip assembly for high voltage IGBT packages. In: UNSPECIFIED pp. 1-5..

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This paper details a co-design and modelling methodology to optimise the flip-chip assembly parameters so that the overall package and system meets performance and reliability specifications for LED lighting applications. A co-design methodology is employed between device level modelling and package level modelling in order enhance the flow of information. As part of this methodology, coupled electrical, thermal and mechniacal predictions are made in order to mitigate underfill dielectric breakdown failure and solder interconnect fatigue failure. Five commercial underfills were selected for investigating the trade-off in materials properties that mitigate underfill electrical breakdown and solder joint fatigue.

Item Type: Conference or Workshop Item (UNSPECIFIED)
Depositing User: Cron Job
Date Deposited: 12 Nov 2018 20:11
Last Modified: 13 Apr 2021 09:30
DOI: 10.1109/THERMINIC.2017.8233847